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Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
CoWare—a design environment for heterogenous hardware/software systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Proceedings of the 6th international workshop on Hardware/software codesign
Getting to the bottom of deep submicron
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Interface exploration for reduced power in core-based systems
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Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Surviving the SOC revolution: a guide to platform-based design
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A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A codesign back-end approach for embedded system design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Algorithms for VLSI Physcial Design Automation
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Computers and Intractability: A Guide to the Theory of NP-Completeness
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Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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High-level power analysis for on-chip networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
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Proceedings of the 42nd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
Proceedings of the 2006 international workshop on System-level interconnect prediction
Physical design implementation of segmented buses to reduce communication energy
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Application specific NoC design
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System level design paradigms: Platform-based design and communication synthesis
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Design space exploration and prototyping for on-chip multimedia applications
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FABSYN: floorplan-aware bus architecture synthesis
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On-Chip Communication Architectures: System on Chip Interconnect
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Integration, the VLSI Journal
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NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
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NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
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Energy/area/delay tradeoffs in the physical design of on-chip segmented bus architecture
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Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we present a point-to-point (P2P) communication synthesis methodology for System-On-Chip (SOC) design. We consider real-time systems where IP selection, mapping and task scheduling are already fixed. Our algorithm takes the communication task graph (CTG) and IP sizes as inputs and automatically synthesizes a P2P communication network, which satisfies the specified deadlines of the application. As main contribution, we first formulate the problem of automatic bitwidth synthesis which minimizes total wirelength and then propose an efficient heuristic to solve it. A key element in our approach is a communication-driven floorplanner which considers the communication energy consumption in the objective function. Experimental results show that, compared to standard shared bus architecture, significant power savings can be achieved by using the P2P scheme and communication-driven floorplanning. For instance, for an H.263 encoder, we estimate 21.6% savings in energy and 15.1% in terms of wiring resources with an area overhead of only 4%.