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IEEE Transactions on Computers
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ACM SIGCOMM Computer Communication Review
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SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
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IPPS '99/SPDP '99 Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing
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ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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Principles and Practices of Interconnection Networks
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
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Proceedings of the 43rd annual Design Automation Conference
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ITNG '07 Proceedings of the International Conference on Information Technology
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Proceedings of the conference on Design, automation and test in Europe
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Integration, the VLSI Journal
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Computers and Electrical Engineering
Area and Power-efficient Innovative Network-on-Chip Architecurte
PDP '10 Proceedings of the 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing
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Proceedings of the Conference on Design, Automation and Test in Europe
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Microprocessors & Microsystems
Scalable load balancing congestion-aware Network-on-Chip router architecture
Journal of Computer and System Sciences
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Microprocessors & Microsystems
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This paper proposes a novel Network-on-Chip architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also provides a power-efficient solution for interconnection network scenarios. Diagonally-linked mesh NoC that uses wormhole packet switching technique implements a high-performance NoC platform to meet both cost and power consumption requirements. The proposed architecture uses an adaptive quasi-minimal routing algorithm so that it can improve average latency and saturation traffic load owing to its flexibility and adaptiveness. Based on these features, a congestion-aware routing algorithm is proposed to balance traffic load so as to alleviate congestion caused by high throughput network activities. Simulation results show that saturation load is improved dramatically for various traffic patterns. Implementation results also show that employing diagonal links is a more area-efficient method for improving network performance than using large buffers. It is shown that congestion-aware router requires negligible cost overhead but provides better throughput. Finally, simulation results also reveal that power consumption in the proposed architecture outperforms traditional mesh networks.