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IEEE Transactions on Parallel and Distributed Systems
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ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
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System-Level Design Techniques for Energy-Efficient Embedded Systems
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Proceedings of the 41st annual Design Automation Conference
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
EDXY - A low cost congestion-aware routing algorithm for network-on-chips
Journal of Systems Architecture: the EUROMICRO Journal
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ICACT'10 Proceedings of the 12th international conference on Advanced communication technology
MAMECTIS'10 Proceedings of the 12th WSEAS international conference on Mathematical methods, computational techniques and intelligent systems
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Journal of Systems Architecture: the EUROMICRO Journal
A simple and efficient input selection function for networks-on-chip
ICDCN'12 Proceedings of the 13th international conference on Distributed Computing and Networking
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Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
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Microprocessors & Microsystems
Cost-effective contention avoidance in a CMP with shared memory controllers
Euro-Par'12 Proceedings of the 18th international conference on Parallel Processing
Scalable load balancing congestion-aware Network-on-Chip router architecture
Journal of Computer and System Sciences
CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems
Proceedings of the Conference on Design, Automation and Test in Europe
CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The performance of Network-on-Chip (NoC) largely depends on the underlying routing techniques, which have two constituencies: output selection and input selection. Previous research on routing techniques for NoC has focused on the improvement of output selection. This paper investigates the impact of input selection, and presents a novel contention-aware input selection (CAIS) technique for NoC that improves the routing efficiency. When there are contentions of multiple input channels competing for the same output channel, CAIS decides which input channel obtains the access depending on the contention level of the upstream switches, which in turn removes possible network congestion. Simulation results with different synthetic and real-life traffic patterns show that, when combined with either deterministic or adaptive output selection, CAIS achieves significant better performance than the traditional first-come-first-served (FCFS) input selection, with low hardware overhead (