On the self-similar nature of Ethernet traffic (extended version)
IEEE/ACM Transactions on Networking (TON)
Proof of a fundamental result in self-similar traffic modeling
ACM SIGCOMM Computer Communication Review
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
Performance Evaluation of the ServerNet R SAN under Self-Similar Traffic
IPPS '99/SPDP '99 Proceedings of the 13th International Symposium on Parallel Processing and the 10th Symposium on Parallel and Distributed Processing
Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
GOAL: a load-balanced adaptive routing algorithm for torus networks
Proceedings of the 30th annual international symposium on Computer architecture
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
Improving routing efficiency for network-on-chip through contention-aware input selection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Prediction-based flow control for network-on-chip traffic
Proceedings of the 43rd annual Design Automation Conference
On-line Fault Detection and Location for NoC Interconnects
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
A Fault tolerant mechanism for handling Permanent and Transient Failures in a Network on Chip
ITNG '07 Proceedings of the International Conference on Information Technology
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
ITNG '07 Proceedings of the International Conference on Information Technology
Congestion-controlled best-effort communication for networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
Area and Power-efficient Innovative Network-on-Chip Architecurte
PDP '10 Proceedings of the 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing
EDXY - A low cost congestion-aware routing algorithm for network-on-chips
Journal of Systems Architecture: the EUROMICRO Journal
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Area and power-efficient innovative congestion-aware Network-on-Chip architecture
Journal of Systems Architecture: the EUROMICRO Journal
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Adaptive routing algorithms have been employed in interconnection networks to improve network throughput and provide better fault tolerance characteristics. However, they can harm performance by disturbing any inherent global load balance through greedy local decisions. This paper proposes a novel scalable load balancing congestion-aware Network-on-Chip (NoC) architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also improves overall network throughput for various traffic scenarios. This congestion control scheme which consists of dynamic input arbitration and adaptive routing path selection is proposed to balance global traffic load distribution so as to alleviate congestion caused by heavy network activities. Furthermore, faulty links information can be broadcasted by existing congestion management control signals to prevent packets from routing through defected areas in order to eliminate potential heavy congestion situations around these regions. Experimental results show that throughput is improved dramatically while maintaining superior latency performance for various traffic patterns. Compared to a baseline router, the proposed congestion management mechanism requires negligible cost overhead but provides better throughput for both mesh and diagonally-linked mesh NoC platforms.