The design and analysis of spatial data structures
The design and analysis of spatial data structures
A two-dimensional topological compactor with octagonal geometry
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Constructing exact octagonal steiner minimal trees
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A new paradigm for general architecture routing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the 41st annual Design Automation Conference
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient octilinear Steiner tree construction based on spanning graphs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A 4-geometry maze router and its application on multiterminal nets
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
DraXRouter: global routing in X-Architecture with dynamic resource assignment
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Highly scalable algorithms for rectilinear and octilinear Steiner trees
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
The Y-architecture: yet another on-chip interconnect solution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
An accurate and efficient probabilistic congestion estimation model in x architecture
Proceedings of the 2007 international workshop on System level interconnect prediction
X-architecture placement based on effective wire models
Proceedings of the 2007 international symposium on Physical design
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement
Integration, the VLSI Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Revisiting fidelity: a case of elmore-based Y-routing trees
Proceedings of the 2008 international workshop on System level interconnect prediction
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm
Integration, the VLSI Journal
Steiner trees for fixed orientation metrics
Journal of Global Optimization
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
Honeycomb-structured computational interconnects and their scalable extension to spherical domains
Proceedings of the 11th international workshop on System level interconnect prediction
Timing-driven non-rectangular obstacles-avoiding routing algorithm for the X-architecture
IMCAS'09 Proceedings of the 8th WSEAS international conference on Instrumentation, measurement, circuits and systems
WSEAS Transactions on Circuits and Systems
A near linear time approximation scheme for Steiner tree among obstacles in the plane
Computational Geometry: Theory and Applications
Rotational steiner ratio problem under uniform orientation metrics
CJCDGCGT'05 Proceedings of the 7th China-Japan conference on Discrete geometry, combinatorics and graph theory
Area and power-efficient innovative congestion-aware Network-on-Chip architecture
Journal of Systems Architecture: the EUROMICRO Journal
Approximation of octilinear steiner trees constrained by hard and soft obstacles
SWAT'06 Proceedings of the 10th Scandinavian conference on Algorithm Theory
Hardness and approximation of octilinear steiner trees
ISAAC'05 Proceedings of the 16th international conference on Algorithms and Computation
Flexibility of steiner trees in uniform orientation metrics
ISAAC'04 Proceedings of the 15th international conference on Algorithms and Computation
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
BonnRoute: Algorithms and data structures for fast and good VLSI routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scalable load balancing congestion-aware Network-on-Chip router architecture
Journal of Computer and System Sciences
Computational complexity for uniform orientation Steiner tree problems
ACSC '13 Proceedings of the Thirty-Sixth Australasian Computer Science Conference - Volume 135
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The X Architecture is an integrated-circuit wiring architecture based on the pervasive use of diagonal wires. Compared with the traditional, currently ubiquitous, Manhattan architecture, the X Architecture demonstrates a wire length reduction of more than 20% and a via reduction of more 30%. Because of the rapidly increasing percentage of delay due to interconnect and the manufacturing challenges due to vias in the nanometer realm, these length and via reductions result simultaneously in a chip performance improvement of 10%, a power reduction of 20%, and a die cost reduction of 30%. Furthermore, the reduction in both wire length and parallel runs on different layers often both reduces die size and improves signal integrity. Remarkably, on virtually every important measure of chip quality, the X Architecture is superior to the Manhattan architecture.While diagonal wiring has been discussed for years, and short diagonal jogs have even been used for years, pervasive diagonal wiring has not been used on an IC before 2002 (to our knowledge). The fundamental reasons for this are not manufacturing limitations, as might be suspected, but EDA limitations, and the changes required to take full advantage of the X Architecture are significant and numerous. In particular, routing must be not only octilinear, but also gridless and non-preferred direction. In addition, significant changes are required at least in floorplanning, placement, global routing, extraction, power routing, clock routing, wire length estimation (e.g., in synthesis), database, graphics, and even data interchange formats. The folklore that 45-degree wiring might not be worth the trouble because it can provide only a 10% reduction in wire length is rooted in the incorrect assumptions that (a) only the router must change, (b) the router must resemble contemporary, preferred-direction, net-at-a-time maze routers, and (c) that wire length is the only major contributor to interconnect delay.In this short paper, we present some of the challenges and opportunities afforded by the X Architecture and show some early results that demonstrate the promise of pervasive, diagonal wiring, reflecting our belief that five years from now, virtually all, high-performance, integrated circuits will use the X Architecture.