Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Constructing exact octagonal steiner minimal trees
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Track assignment: a desirable intermediate step between global routing and detailed routing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
A New Effective Congestion Model in Floorplan Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Multilevel routing with antenna avoidance
Proceedings of the 2004 international symposium on Physical design
A new paradigm for general architecture routing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient octilinear Steiner tree construction based on spanning graphs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
Probabilistic congestion model considering shielding for crosstalk reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Computational Geometry: Algorithms and Applications
Computational Geometry: Algorithms and Applications
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An effective congestion-driven placement framework
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Provably good performance-driven global routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been proposed for high-performance integrated circuits. In this paper, we present a performance-driven X-architecture router based on a novel multilevel framework, called PIXAR. To fully consider performance-driven routing and take advantage of the X-architecture, PIXAR applies a novel multilevel routing framework, which adopts a two-stage technique of top-down uncoarsening followed by bottom-up coarsening, with a trapezoid-shaped track routing embedded between the two stages to assign long, straight diagonal segments for wirelength reduction. We also propose a performance-driven X-Steiner tree algorithm based on the delaunay triangulations to construct routing tree for performance optimization. Compared with the state-of-the-art work, PIXAR achieves 100% routing completion for all circuits while reduced the net delay.