A predictive distributed congestion metric and its application to technology mapping
Proceedings of the 2004 international symposium on Physical design
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A buffer planning algorithm with congestion optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A fast congestion estimator for routing with bounded detours
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Interconnect capacitance estimation for FPGAs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power estimation techniques for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient technology mapping algorithm targeting routing congestion under delay constraints
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Prediction and reduction of routing congestion
Proceedings of the 2006 international symposium on Physical design
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Novel full-chip gridless routing considering double-via insertion
Proceedings of the 43rd annual Design Automation Conference
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
An accurate and efficient probabilistic congestion estimation model in x architecture
Proceedings of the 2007 international workshop on System level interconnect prediction
Fast and accurate routing demand estimation for efficient routability-driven placement
Proceedings of the conference on Design, automation and test in Europe
Evaluation, prediction and reduction of routing congestion
Microelectronics Journal
Using metro-on-chip in physical design flow for congestion and routability improvement
Microelectronics Journal
Metal-density driven placement for cmp variation and routability
Proceedings of the 2008 international symposium on Physical design
A fast congestion estimator for routing with bounded detours
Integration, the VLSI Journal
Proceedings of the 45th annual Design Automation Conference
An integrated nonlinear placement framework with congestion and porosity aware buffer planning
Proceedings of the 45th annual Design Automation Conference
A combinatorial congestion estimation approach with generalized detours
Computers & Mathematics with Applications
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
A Parallel Simulated Annealing Approach for Floorplanning in VLSI
ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A multilevel congestion-based global router
VLSI Design
Stability and scalability in global routing
Proceedings of the System Level Interconnect Prediction Workshop
GLARE: global and local wiring aware routability evaluation
Proceedings of the 49th Annual Design Automation Conference
Can pin access limit the footprint scaling?
Proceedings of the 49th Annual Design Automation Conference
A methodology for the early exploration of design rules for multiple-patterning technologies
Proceedings of the International Conference on Computer-Aided Design
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing
Proceedings of the International Conference on Computer-Aided Design
Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits
Proceedings of the 50th Annual Design Automation Conference
Routing congestion estimation with real design constraints
Proceedings of the 50th Annual Design Automation Conference
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Design routability is a major concern in the application-specific design flow, particularly with today's increasingly aggressive process technology nodes. Increased die areas, cell densities, routing layers, and net count all contribute to complex interconnect requirements, which can significantly deteriorate performance and sometimes lead to unroutable solutions. Congestion analysis and optimization must be performed early in the design cycle to improve routability. This paper presents a congestion estimation algorithm for a placed net list. We propose a net-based stochastic model for computing expected horizontal and vertical track usage, which considers routing blockages. The main advantages of this algorithm are its accuracy and fast runtime. We show that the congestion estimated by this algorithm correlates well with postroute congestion and present experimental results of subsequent congestion minimization based on this algorithm