PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Timing closure based on physical hierarchy
Proceedings of the 2002 international symposium on Physical design
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Coping with Latency in SOC Design
IEEE Micro
Congestion reduction in traditional and new routing architectures
Proceedings of the 13th ACM Great Lakes symposium on VLSI
High-Speed QDI Asynchronous Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
A High-Speed Clockless Serial Link Transceiver
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
On-chip communication design: roadblocks and avenues
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Dragon2005: large-scale mixed-size placement tool
Proceedings of the 2005 international symposium on Physical design
A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Fast Asynchronous Shift Register for Bit-Serial Communication
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Optimization techniques for FPGA-based wave-pipelined DSP blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electronic Design Automation for Integrated Circuits Handbook - 2 Volume Set
Electronic Design Automation for Integrated Circuits Handbook - 2 Volume Set
Evaluation, prediction and reduction of routing congestion
Microelectronics Journal
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Integration, the VLSI Journal
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Routability, signal integrity and manufacturability are important issues in physical design and congestion reduction is a widely used method for ameliorating these problems in current design methodologies. Besides, routing congestion may create large delays in detoured global wires that can be avoided by congestion reduction. In recent years, asynchronous serial transceivers are proposed for data transmission in network-on-chip systems to improve the performance of global wires. However the asynchronous transceivers have not been used for reducing the congestion and improving the routability in the physical design flow. In this paper, a new methodology is presented in which regular nets are multiplexed by asynchronous serial transceivers in the physical design flow in order to improve routing congestion and design routability. Experimental results show that for attempted benchmarks, the congestion is reduced by 18.97%, the routability is increased by 21.57% on average and total wirelength is decreased up to 9.05%. However, the overhead in power consumption and computation time are 0.12% and 10.01%, respectively, on average.