The Steiner tree problem in orientation metrics
Journal of Computer and System Sciences
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Preferred direction Steiner trees
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Improved cut sequences for partitioning based placement
Proceedings of the 38th annual Design Automation Conference
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
An Exact Algorithm for the Uniformly-Oriented Steiner Tree Problem
ESA '02 Proceedings of the 10th Annual European Symposium on Algorithms
Highly scalable algorithms for rectilinear and octilinear Steiner trees
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
The Y-architecture: yet another on-chip interconnect solution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A global wiring paradigm for deep submicron design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing by new approximation algorithms for multicommodity flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DraXRouter: global routing in X-Architecture with dynamic resource assignment
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Diagonal routing in high performance microprocessor design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Using metro-on-chip in physical design flow for congestion and routability improvement
Microelectronics Journal
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, routing, and routing architecture all contribute. Previous work has shown that different placement tools can have substantially different demands for each routing layer; our objective is to develop methods that allow "tuning" of interconnect topologies to match routing resources.We focus on congestion minimization for both Manhattan and non-Manhattan routing architectures, and have two main contributions. First, we combine prior heuristics for non-Manhattan Steiner trees and Preferred Direction Steiner trees into a hybrid approach that can handle arbitrary routing directions, via minimization, and layer assignment of edges simultaneously. Second, we present an effective method to adjust Steiner tree topologies to match routing demand to resource, resulting in lower congestion and better routability.