Benchmarking for large-scale placement and beyond

Authors:
Saurabh N. Adya;Mehmet C. Yildiz;Igor L. Markov;Paul G. Villarrubia;Phiroze N. Parakh;Patrick H. Madden
Affiliations:
The University of Michigan, Ann Arbor, MI;SUNY Binghamton, Binghamton, NY;The University of Michigan, Ann Arbor, MI;IBM Corp., Austin, TX;Monterey Design Systems, Sunnyvale, CA;SUNY Binghamton, Binghamton, NY
Venue:
Proceedings of the 2003 international symposium on Physical design
Year:
2003

Citing 43
Cited 16

Analytical placement: A linear or a quadratic objective function?

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing driven placement for large standard cell circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Quantified suboptimality of VLSI layout heuristics

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Multilevel hypergraph partitioning: application in VLSI domain

DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning

DAC '97 Proceedings of the 34th annual Design Automation Conference
Partitioning-based standard-cell global placement with an exact objective

Proceedings of the 1997 international symposium on Physical design
The ISPD98 circuit benchmark suite

ISPD '98 Proceedings of the 1998 international symposium on Physical design
Generic global placement and floorplanning

DAC '98 Proceedings of the 35th annual Design Automation Conference
Congestion driven quadratic placement

DAC '98 Proceedings of the 35th annual Design Automation Conference
Hypergraph partitioning for VLSI CAD: methodology for heuristic development, experimentation and reporting

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Requirements for models of achievable routing

ISPD '00 Proceedings of the 2000 international symposium on Physical design
Why interconnect prediction doesn't work

SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Timing-driven placement based on partitioning with dynamic cut-net control

Proceedings of the 37th Annual Design Automation Conference
Can recursive bisection alone produce routable placements?

Proceedings of the 37th Annual Design Automation Conference
The role of custom design in ASIC Chips

Proceedings of the 37th Annual Design Automation Conference
Transformational placement and synthesis

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Improved algorithms for hypergraph bipartitioning

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A performance-driven standard-cell placer based on a modified force-directed algorithm

Proceedings of the 2001 international symposium on Physical design
Estimating routing congestion using probabilistic analysis

Proceedings of the 2001 international symposium on Physical design
Improved cut sequences for partitioning based placement

Proceedings of the 38th annual Design Automation Conference
Timing driven placement using physical net constraints

Proceedings of the 38th annual Design Automation Conference
Design and implementation of move-based heuristics for VLSI hypergraph partitioning

Journal of Experimental Algorithmics (JEA)
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction

SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
An effective congestion driven placement framework

Proceedings of the 2002 international symposium on Physical design
Consistent placement of macro-blocks using floorplanning and standard-cell placement

Proceedings of the 2002 international symposium on Physical design
Routability driven white space allocation for fixed-die standard-cell placement

Proceedings of the 2002 international symposium on Physical design
Min-max placement for large-scale timing optimization

Proceedings of the 2002 international symposium on Physical design
On metrics for comparing routability estimation methods for FPGAs

Proceedings of the 39th annual Design Automation Conference
Predictable routing

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel optimization for large-scale circuit placement

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A force-directed maze router

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimality, scalability and stability study of partitioning and placement algorithms

Proceedings of the 2003 international symposium on Physical design
A novel net weighting algorithm for timing-driven placement

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Timing-driven placement using design hierarchy guided constraint generation

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Metrics for structural logic synthesis

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Free space management for cut-based placement

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A linear-time heuristic for improving network partitions

DAC '82 Proceedings of the 19th Design Automation Conference
Multi-level placement for large-scale mixed-size IC designs

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Optimality and scalability study of existing placement algorithms

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Hypergraph partitioning with fixed vertices [VLSI CAD]

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal partitioners and end-case placers for standard-cell layout

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reporting of standard cell placement results

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Congestion reduction in traditional and new routing architectures

Proceedings of the 13th ACM Great Lakes symposium on VLSI
Boosting: Min-Cut Placement with Improved Signal Delay

Proceedings of the conference on Design, automation and test in Europe - Volume 2
A study of netlist structure and placement efficiency

Proceedings of the 2004 international symposium on Physical design
Constructive benchmarking for placement

Proceedings of the 14th ACM Great Lakes symposium on VLSI
On legalization of row-based placements

Proceedings of the 14th ACM Great Lakes symposium on VLSI
Fractional Cut: Improved Recursive Bisection Placement

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Trade-off Oriented Placement Tool

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Large-Scale Circuit Placement: Gap and Promise

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Combinatorial techniques for mixed-size placement

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evaluation of placer suboptimality via zero-change netlist transformations

Proceedings of the 2005 international symposium on Physical design
Large-scale circuit placement

ACM Transactions on Design Automation of Electronic Systems (TODAES)
On structure and suboptimality in placement

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal placement by branch-and-price

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Effective linear programming based placement methods

Proceedings of the 2006 international symposium on Physical design
Zephyr: a static timing analyzer integrated in a trans-hierarchical refinement design flow

PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Quantified Score

Hi-index	0.00

Visualization

Abstract

Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results. These advances have been supported by non-trivial benchmarking infrastructure, and future achievements are set to draw on benchmarking as well. In this paper we review motivations for benchmarking, especially for commercial EDA, analyze available benchmarks, and point out major pitfalls in benchmarking. We outline major outstanding problems and discuss the future of placement benchmarking. Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.