Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Fast evaluation of sequence pair in block placement by longest common subsequence computation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
A force-directed macro-cell placer
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal partitioners and end-case placers for standard-cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Constrained "Modern" Floorplanning
Proceedings of the 2003 international symposium on Physical design
An algebraic multigrid solver for analytical placement with layout based clustering
Proceedings of the 40th annual Design Automation Conference
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Unified quadratic programming approach for mixed mode placement
Proceedings of the 2005 international symposium on Physical design
FastPlace: an analytical placer for mixed-mode designs
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Faster and better global placement by a new transportation algorithm
Proceedings of the 42nd annual Design Automation Conference
An analytic placer for mixed-size placement and timing-driven placement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Multilevel expansion-based VLSI placement with blockages
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Engineering details of a stable force-directed placer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
Proceedings of the 2006 international workshop on System-level interconnect prediction
A robust detailed placement for mixed-size IC designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
FastPlace 2.0: an efficient analytical placer for mixed-mode designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Multi-level placement for large-scale mixed-size IC designs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Robust mixed-size placement under tight white-space constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Optimal cell flipping in placement and floorplanning
Proceedings of the 43rd annual Design Automation Conference
On whitespace and stability in physical synthesis
Integration, the VLSI Journal
Mixed-size placement with fixed macrocells using grid-warping
Proceedings of the 2007 international symposium on Physical design
A network-flow approach to timing-driven incremental placement for ASICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Optimizing wirelength and routability by searching alternative packings in floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Handling complexities in modern large-scale mixed-size placement
Proceedings of the 46th Annual Design Automation Conference
Interactive circuit diagram visualization
CGIM '08 Proceedings of the Tenth IASTED International Conference on Computer Graphics and Imaging
An analytical placer for mixed-size 3D placement
Proceedings of the 19th international symposium on Physical design
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
Quantifying academic placer performance on custom designs
Proceedings of the 2011 international symposium on Physical design
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-stage detailed placement algorithm for large-scale mixed-mode layout design
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part IV
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While a number of recent works address large-scale standard-cellplacement, they typically assume that all macros are fixed.Floorplanning techniques are very good at handling macros, but donot scale to hundreds of thousands of placeable objects. Thereforewe combine floorplanning techniques with placement techniques in adesign flow that solves the more general placement problem. Ourwork shows how to place macros consistently with large numbers ofsmall standard cells. Our techniques can also be used to guidecircuit designers who prefer to place macros by hand.The proposed flow relies on an arbitrary black-box standard-cellplacer to obtain an initial placement and then removes possibleoverlaps using a fixed-outline floorplanner. This results in validplacements for macros, which are considered fixed. Remainingstandard cells are then placed by another call to the standard-cellplacer. Empirical evaluation on ibm benchmarks shows, in mostcases, wirelength improvements of 10%-50% compared to CadenceQPlace, as well as runtime improvements.