Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Algorithms for drawing graphs: an annotated bibliography
Computational Geometry: Theory and Applications
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Drawing graphs: methods and models
Drawing graphs: methods and models
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Graph Drawing: Algorithms for the Visualization of Graphs
Graph Drawing: Algorithms for the Visualization of Graphs
Crossing Reduction by Windows Optimization
GD '02 Revised Papers from the 10th International Symposium on Graph Drawing
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Formal verification of a PowerPC microprocessor
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Recursive bi-partitioning of netlists for large number of partitions
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Orthogonal hypergraph routing for improved visibility
Proceedings of the 14th ACM Great Lakes symposium on VLSI
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Automated visualization of circuits is an important research area in electronic design automation. In contrast to the numerous papers and work done on graph and hypergraph drawing on equal size nodes, this paper presents a framework to efficiently cope with nodes that are orders of magnitudes different in size. To improve the clarity of the drawing a crossing reduction step and a fast routing heuristic are applied which try to avoid unnecessary crossings and bends within the wiring. Experimental results are provided which show that the run time remains small enough to drive an interactive tool even on very large circuit benchmarks.