Journal of Information Processing
Algorithms for drawing graphs: an annotated bibliography
Computational Geometry: Theory and Applications
Arc crossing minimization in hierarchical digraphs with tabu search
Computers and Operations Research
A Polyhedral Approach to the Multi-Layer Crossing Minimization Problem
GD '97 Proceedings of the 5th International Symposium on Graph Drawing
k-Layer Straightline Crossing Minimization by Speeding Up Sifting
GD '00 Proceedings of the 8th International Symposium on Graph Drawing
Level Assignment for Displaying Combinational Logic
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Minimizing crossings in hierarchical digraphs with a hybridized genetic algorithm
Journal of Heuristics
Interactive circuit diagram visualization
CGIM '08 Proceedings of the Tenth IASTED International Conference on Computer Graphics and Imaging
k-level crossing minimization is NP-hard for trees
WALCOM'11 Proceedings of the 5th international conference on WALCOM: algorithms and computation
GD'04 Proceedings of the 12th international conference on Graph Drawing
Grid sifting: Leveling and crossing reduction
Journal of Experimental Algorithmics (JEA)
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The number of edge crossings is a commonly accepted measure to judge the "readability" of graph drawings. In this paper we present a new algorithm for high quality multi-layer straight-line crossing minimization. The proposed method uses a local optimization technique where subsets of nodes and edges are processed exactly. The algorithm uses optimization on a window applied in a manner, similar to those used in the area of formal verification of logic circuits. In contrast to most existing heuristics, more than two layers are considered simultaneously. The algorithm tries to reduce the total number of crossings based on an initial placement of the nodes and can thus also be used in a post-processing step. Experiments are given to demonstrate the efficacy of the proposed technique on benchmarks from the area of circuit design.