Functional verification methodology of Chameleon processor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal methods: state of the art and future directions
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
Using complete-1-distinguishability for FSM equivalence checking
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
MORE: an alternative implementation of BDD packages by multi-operand synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Optimizing designs containing black boxes
DAC '97 Proceedings of the 34th annual Design Automation Conference
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
A pseudo-hierarchical methodology for high performance microprocessor design
Proceedings of the 1997 international symposium on Physical design
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
On Variable Ordering and Decomposition Type Choice in OKFDDs
IEEE Transactions on Computers
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Ordered Binary Decision Diagrams and Minimal Trellises
IEEE Transactions on Computers
Using complete-1-distinguishability for FSM equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Combinational and sequential equivalence checking
Logic Synthesis and Verification
K*BMDs: A New Data Structure for Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A symbolic core approach to the formal verification of integrated mixed-mode applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Safe integration of parameterized IP
Integration, the VLSI Journal - Special issue: IP and design reuse
New methods and coverage metrics for functional verification
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Abstraction and refinement techniques in automated design debugging
Proceedings of the conference on Design, automation and test in Europe
Interactive circuit diagram visualization
CGIM '08 Proceedings of the Tenth IASTED International Conference on Computer Graphics and Imaging
A symbolic modelling approach for the formal verification of integrated mixed-mode systems
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
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This paper presents the use of formal methods in the design of a PowerPC microprocessor. The chosen methodology employs two independently developed design views, a register-transfer level specification for efficient system simulation and a transistor level implementation geared toward maximal processor performance. A BDD-based verification tool is used to functionally compare the two views which essentially validates the transistor-level implementation with respect to any functional simulation/verification performed at the register-transfer level. We show that a tight integration of the verification approach into the overall design methodology allows the formal verification of complex microprocessor implementations without compromising the design process or performance of the resulting system.