Optimizing designs containing black boxes

Authors:
Tai-Hung Liu;Khurram Sajid;Adnam Aziz;Vigyan Singhal
Affiliations:
Electrical and Computer Engineering, The University of Texas, Austin TX;Electrical and Computer Engineering, The University of Texas, Austin TX;Electrical and Computer Engineering, The University of Texas, Austin TX;Cadence Berkeley Labs, Cadence, Berkeley, CA
Venue:
DAC '97 Proceedings of the 34th annual Design Automation Conference
Year:
1997

Citing 11
Cited 5

Don't cares in multi-level network optimization

Don't cares in multi-level network optimization
Model checking, abstraction, and compositional verification

Model checking, abstraction, and compositional verification
BooleDozer: logic synthesis for ASICs

IBM Journal of Research and Development
Modeling hierarchical combinational circuits

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A Practical Decision Procedure for Arithmetic with Function Symbols

Journal of the ACM (JACM)
Synthesis and Optimization of Digital Circuits

Synthesis and Optimization of Digital Circuits
Introduction To Automata Theory, Languages, And Computation

Introduction To Automata Theory, Languages, And Computation
Logic Minimization Algorithms for VLSI Synthesis

Logic Minimization Algorithms for VLSI Synthesis
Sequential Circuit Design Using Synthesis and Optimization

ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Formal verification of a PowerPC microprocessor

ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Design replacements for sequential circuits

Design replacements for sequential circuits

Intellectual property protection by watermarking combinational logic synthesis solutions

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Optimizing designs containing black boxes

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking

FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Pattern-based verification of connections to intellectual property cores

Integration, the VLSI Journal
Don't cares in logic minimization of extended finite state machines

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

We define a notion of equivalence for designs containingblack boxes i.e., components whose functionality is notknown; these arise naturally in the course of hierarchicaldesign. Using this notion, we describe a sound andcomplete methodology for optimizing such designs.