Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A fully implicit algorithm for exact state minimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Modeling hierarchical combinational circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Detection of symmetry of Boolean functions represented by ROBDDs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Optimizing designs containing black boxes
DAC '97 Proceedings of the 34th annual Design Automation Conference
Designing systems-on-chip using cores
Proceedings of the 37th Annual Design Automation Conference
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model
ATS '98 Proceedings of the 7th Asian Test Symposium
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model
ATS '01 Proceedings of the 10th Asian Test Symposium
On automatic-verification pattern generation for SoC with port-order fault model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Verification of designs containing pre-designed cores is a challenging topic in modern IC design, since traditional approaches generally do not use the information that parts of the design (like IP cores) are already verified. The port order fault model (POF) has recently been introduced for detecting design errors occurring during integration of a core into a system-on-chip or during test logic insertion. In this work, we generate verification patterns with 100% coverage of a sub-class of POF, called 2-POF. We provide theoretical arguments and experimental results backing the efficiency of these patterns also for detecting higher-order POFs. Moreover, verification pattern sets generated by our approach are more compact compared to the results published before.