Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
Minimizing Test Time by Exploiting Parallelism in Macro Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Reconfiguration techniques for a single scan chain
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Microprocessor based testing for core-based system on chip
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
System chip test: how will it impact your design?
Proceedings of the 37th Annual Design Automation Conference
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
Analysis and minimization of test time in a combined BIST and external test approach
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay fault testing of IP-based designs via symbolic path modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
Test Bus Sizing for System-on-a-Chip
IEEE Transactions on Computers
The design and optimization of SOC test solutions
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Approximation of a Geometric Set Covering Problem
ISAAC '01 Proceedings of the 12th International Symposium on Algorithms and Computation
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On Test Scheduling for Core-Based SOCs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Scan Test Sequencing Hardware for Structural Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
Journal of Electronic Testing: Theory and Applications
Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Pattern-based verification of connections to intellectual property cores
Integration, the VLSI Journal
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of reconfigurable access wrappers for embedded core based SoC test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
IEEE Transactions on Computers
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
Test Infrastructure Design for the Nexperia" Home Platform PNX8550 System Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Delay Fault Testing of Core-Based Systems-on-a-Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two efficient methods to reduce power and testing time
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs
IEEE Transactions on Computers
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Analysis of the test data volume reduction benefit of modular SOC testing
Proceedings of the conference on Design, automation and test in Europe
A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling
Journal of Electronic Testing: Theory and Applications
The efficient TAM design for core-based SOCs testing
WSEAS Transactions on Circuits and Systems
WSEAS Transactions on Circuits and Systems
An efficient scheduling algorithm based on multi-frequency tam for SOC testing
WSEAS Transactions on Circuits and Systems
DX-compactor: distributed X-compaction for SoCs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On-chip support for NoC-based SoC debugging
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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The size of the test vector set forms a significant factor in the overall production costs of ICs, as it defines the test applicationtime and the required pin memory size of the test equipment. Large core-based ICs often require a very large test vector setfor a high test coverage. This paper deals with the design of scan chains as transport mechanism for test patterns from IC pinsto embedded cores and vice versa. The number of pins available to accommodate scan test is given, as well as the number ofscan test patterns and scannable flip flops of each core. We present and analyze three scan chain architectures for core-basedICs, which aim at a minimum test vector set size. We give experimental results of the three architectures for an industrial IC.Furthermore we analyze the test time consequences of reusing cores with fixed internal scan chains in multiple ICs with varyingdesign parameters.