Layout driven selecting and chaining of partial scan flip-flops
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Test Bus Sizing for System-on-a-Chip
IEEE Transactions on Computers
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
ATS '01 Proceedings of the 10th Asian Test Symposium
Efficient Wrapper/TAM Co-Optimization for Large SOCs
Proceedings of the conference on Design, automation and test in Europe
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Cluster-Based Test Architecture Design for System-on-Chip
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Infrastructure Design for the Nexperia" Home Platform PNX8550 System Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
A wiring-aware approach to minimizing built-in self-test overhead
Journal of Computer Science and Technology
Wafer-level modular testing of core-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper extends existing SOC test architecture design approaches that minimize required tester vector memory depth and test application time, with the capability to minimize the wire length required by the test architecture. We present a simple, yet effective wire length cost model for test architectures together with a new test architecture design algorithm that minimizes both test time and wire length. The user specifies the relative weight of the costs of test time versus wire length. In an integrated fashion, the algorithm partitions the total available TAM width over individual TAMs, assigns the modules to these TAMs, and orders the modules within one TAM such that the total cost is minimized. Experimental results on five benchmark SOCs show that we can obtain savings of up to 86% in wiring costs at the expense of 4% in test time.