Proceedings of the 39th annual Design Automation Conference
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
Journal of Electronic Testing: Theory and Applications
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
Defect-Aware SOC Test Scheduling
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Note on System-on-Chip Test Scheduling Formulation
Journal of Electronic Testing: Theory and Applications
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Delay Fault Testing of Core-Based Systems-on-a-Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
FITS: An Integrated ILP-Based Test Scheduling Environment
IEEE Transactions on Computers
InTeRail: A Test Architecture for Core-Based SOCs
IEEE Transactions on Computers
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Power-constrained test scheduling for multi-clock domain SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Abort-on-fail based test scheduling
Journal of Electronic Testing: Theory and Applications
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers
Proceedings of the conference on Design, automation and test in Europe
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Low-power multi-core ATPG to target concurrency
Integration, the VLSI Journal
Wrapper and TAM co-optimization for reuse of SoC functional interconnects
Proceedings of the conference on Design, automation and test in Europe
WSEAS Transactions on Circuits and Systems
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
SoC test scheduling algorithm using ACO-based rectangle packing
ICIC'06 Proceedings of the 2006 international conference on Intelligent computing: Part II
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
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A method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based System-On-Chip (SOC) designs is presented in this paper. The primary objective for concurrent SOC test is to reduce test application time. The methodology used in this paper is not limited to any specific Test Access Mechanism (TAM).Additionally, it can also be applied for test budgeting during the design phase to obtain a tradeoff between test application time and SOC pins needed. In this paper, the above problem is formulated as a well-known 2-dimensional bin-packing problem.A best-fit heuristic algorithm is employed to obtain satisfactory results as demonstrated in Section 3.