Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems
ATS '99 Proceedings of the 8th Asian Test Symposium
SOC Test Scheduling Using Simulated Annealing
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On the Use of k-tuples for SoC Test Schedule Representation
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
SoC test scheduling using the B-tree based floorplanning technique
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Multiple-constraint driven system-on-chip test time optimization
Journal of Electronic Testing: Theory and Applications
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SoC test scheduling algorithm using ACO-based rectangle packing
ICIC'06 Proceedings of the 2006 international conference on Intelligent computing: Part II
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
WSEAS Transactions on Circuits and Systems
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This paper presents a Genetic algorithm (GA) based solution to co-optimize test scheduling and wrapper design for core based SOCs. Core testing solutions are generated as a set of wrapper configurations, represented as rectangles with width equal to the number of TAM (Test Access Mechanism) channels and height equal to the corresponding testing time. A locally optimal best-fit heuristic based bin packing algorithm has been used to determine placement of rectangles minimizing the overall test times, whereas, GA has been utilized to generate the sequence of rectangles to be considered for placement. Experimental result on ITC'02 benchmark SOCs shows that the proposed method provides better solutions compared to the recent works reported in the literature.