Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
SoC test scheduling using the B-tree based floorplanning technique
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Power-constrained test scheduling for multi-clock domain SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers
Proceedings of the conference on Design, automation and test in Europe
Wafer-level modular testing of core-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
WSEAS Transactions on Circuits and Systems
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
IEICE - Transactions on Information and Systems
Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
Microprocessor based self schedule and parallel BIST for system-on-a-chip
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
Computers and Electrical Engineering
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We propose an SOC test scheduling method based onsimulated annealing. In our method, the test scheduling isformulated as a two-dimensional bin packing problem (rectanglepacking) and a data structure called a sequence pair is used torepresent the placement of the rectangles. Simulated annealingis used to find the optimal test schedule by altering an initialsequence pair and changing the width of the core wrapper. Wealso propose a method of wrapper design for cores withoutinternal scan chains. Experiments are conducted on ITC'02benchmarks, showing that overall the proposed method providesbetter solutions compared to earlier methods.