An introduction to genetic algorithms
An introduction to genetic algorithms
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
A Unifying Methodology for Intellectual Property and Custom Logic Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Proceedings of the 40th annual Design Automation Conference
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems
ATS '99 Proceedings of the 8th Asian Test Symposium
Test Power: a Big Issue in Large SOC Designs
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
SOC Test Scheduling Using Simulated Annealing
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On the Use of k-tuples for SoC Test Schedule Representation
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Adapting an SoC to ATE Concurrent Test Capabilities
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
SoC test scheduling using the B-tree based floorplanning technique
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Multiple-constraint driven system-on-chip test time optimization
Journal of Electronic Testing: Theory and Applications
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs
IEEE Transactions on Computers
Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
SoC test scheduling algorithm using ACO-based rectangle packing
ICIC'06 Proceedings of the 2006 international conference on Intelligent computing: Part II
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Increasing complexity of System-on-Chip (SOC) has encouraged the engineers to design versatile automated test equipments (ATE) that can drive simultaneously different data channels at different data rates so that overall test cost can be reduced. Devices like Agilent 93000 series tester and Tiger system from Teradyne provide such flexibility to drive different channels at different data rates. Number of tester channels with higher data rate is limited due to different constraints like power rating of the SOCs, limitation of scan frequency, complexity of ATE etc. Hence proper utilization of the tester channels to reduce test time and thereby test cost is important. In this paper we provide a Genetic algorithm based approach for SOC-level TAM architecture optimization that minimizes testing time considering two different data rates for ATE channels. Our approach achieves better results than those reported in the literature. Experimental results show that the maximum improvement of 40.99% in testing time can be achieved. We have also addressed the issue of power constrained testing.