A Unifying Methodology for Intellectual Property and Custom Logic Testing

Path delay fault testing of ICs with embedded intellectual property blocks

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Test Cycle Count Reduction in a Parallel Scan BIST Environment

Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98

A bypass scheme for core-based system fault testing

Proceedings of the conference on Design, automation and test in Europe

Structural Fault Testing of Embedded Cores Using Pipelining

Journal of Electronic Testing: Theory and Applications

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

Journal of Electronic Testing: Theory and Applications

Testing Core-Based Systems: A Symbolic Methodology

IEEE Design & Test

A structured test re-use methodology for core-based system chips

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Modular logic built-in self-test for IP cores

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A novel test methodology for core-based system LSIs and a testing time minimization problem

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Constraint Driven Pin Mapping for Concurrent SOC Testing

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Testing Embedded Cores Using Partial Isolation Rings

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

1.3 Parallelism in Structural Fault Testing of Embedded Cores

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Modifying User-Defined Logic for Test Access to Embedded Cores

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Test Requirements for Embedded Core-based Systems and IEEE P1500

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Partial Core Encryption for Performance-Efficient Test of SOCs

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

InTeRail: A Test Architecture for Core-Based SOCs

IEEE Transactions on Computers

Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

A non-intrusive isolation approach for soft cores

Proceedings of the conference on Design, automation and test in Europe

A genetic algorithm based approach for system-on-chip test scheduling using dual speed TAM with power constraint

WSEAS Transactions on Circuits and Systems

Fault isolation for nonisolated blocks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems