Blocking in a system on a chip
IEEE Spectrum
IEEE Spectrum
Introducing Core-Based System Design
IEEE Design & Test
A Unifying Methodology for Intellectual Property and Custom Logic Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
A Unified Interface for Scan Test Generation Based on STIL
Proceedings of the IEEE International Test Conference
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
1.1 Test methodology for embedded cores which protects intellectual property
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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Chips comprising reusable cores, i.e. pre-designedIntellectual Property (IP) blocks, have become an importantpart of IC-based system design. Using embedded coresenables the design of high-complexity system-chips withdensities as high as millions of gates on a single die. Theincrease in using pre-designed IP cores in system-chips addsto the complexity of test. To test system-chips adequately, testsolutions need to be incorporated into individual cores andthen the tests from individual cores need to be scheduled andassembled into a chip level test. However with the increasedusage of cores from multiple and diverse sources, it isessential to create standard mechanisms to make core testplug-and-play possible. This paper discusses in general thechallenges in testing core-based system-chips and describestheir corresponding test solutions. It concentrates on thecommon test requirements and introduces the on-goingstandardization efforts, specifically under IEEE PI.500Working Group, which is meant to standardize the interfacebetween a core test and its host the System-on-Chip.