High-Level Test Generation for VLSI
Computer
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Optimal Space Compaction of Test Responses
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay fault testing of IP-based designs via symbolic path modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Online BIST for Embedded Systems
IEEE Design & Test
A Fault Tolerant Approach to Microprocessor Design
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Delay Fault Testing of Designs with Embedded IP Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Test Requirements for Embedded Core-based Systems and IEEE P1500
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computers
Deployment of Better Than Worst-Case Design: Solutions and Needs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Instruction-level test methodology for CPU core self-testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Ultra low-cost defect protection for microprocessor pipelines
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Architecting a reliable CMP switch architecture
ACM Transactions on Architecture and Code Optimization (TACO)
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Test time minimization for hybrid BIST of core-based systems
Journal of Computer Science and Technology
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 4.11 |
Trends in integrated circuit design have made testing ICs more difficult than ever before. Yet test is essential: Although IC design and manufacturing methods obviously contribute to quality, high-quality ICs rely on high-quality test. And testing is a major contributor to the cost of manufacturing and maintaining ICs. The industry does have well-developed fault models and test-generation methods, and these methods are widely supported by design tools. However, their applicability to today's increasingly fast and complex circuits is limited by practical cost considerations. Design-for-test techniques, especially scan design and built-in self-test, can provide a satisfactory solution in many instances. Developments in IC technology continue to pose new testing challenges, however. A noteworthy example is the problem of efficiently testing predesigned, embedded components, or cores. Widespread use of cores is a new phenomenon, and it creates some challenging testing problems. This tutorial examines the market and technology trends affecting the testing of integrated circuits, with emphasis on the role of cores and built-in self-test. The authors explain manufacturing testing, as opposed to design testing, which happens before manufacturing, and on-line testing, which happens after.