Test-set preserving logic transformations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An Effective BIST Scheme for Arithmetic Logic Units
Proceedings of the IEEE International Test Conference
Minimal Delay Test Sets for Unate Gate Networks
ATS '96 Proceedings of the 5th Asian Test Symposium
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
1.1 Test methodology for embedded cores which protects intellectual property
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Properties of the input pattern fault model
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
High-level test generation using physically-induced faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
The Design of Easily Testable VLSI Array Multipliers
IEEE Transactions on Computers
Derivation of Minimum Test Sets for Unate Logical Circuits
IEEE Transactions on Computers
Complete Test Sets for Logic Functions
IEEE Transactions on Computers
Universal Test Sets for Logic Networks
IEEE Transactions on Computers
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams
Proceedings of the 37th Annual Design Automation Conference
Logic Design Validation via Simulation and Automatic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Delay fault testing of IP-based designs via symbolic path modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay Fault Testing of Designs with Embedded IP Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On the Evaluation of Arbitrary Defect Coverage of Test Sets
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling
ITC '99 Proceedings of the 1999 IEEE International Test Conference
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
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Conventional ATPG cannot effectively handle designsemploying IP circuits (cores) whose implementation detailsare either unknown, unavailable, or subject to change. Anew ATPG program RIBTEC for such designs is describedthat employs a functional (behavioral) fault model based ona class of non-exhaustive "universal" test sets. Given acircuit's high-level block structure, RIBTEC constructs auniversal test set for each block from its functionaldescription in such a way that realization-independence ofthe blocks is ensured. Experimental results are presented forrepresentative datapath circuits, which show that RIBTECachieves very high fault coverage and an exceptionally highlevel of realization independence.