Technology mapping for field-programmable gate arrays using integer programming
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Hierarchical timing analysis using conditional delays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An approximate timing analysis method for datapath circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
General modeling and technology-mapping technique for LUT-based FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
A general approach for regularity extraction in datapath circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
From Design Validation to Hardware Testing: A Unified Approach
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Synthesis of single-output space compactors with application to scan-based IP cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
General technology mapping for field-programmable gate arrays based on lookup tables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Computer Science and Technology
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Behavioral Fault Modeling in a VHDL Synthesis Environment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Width Compression for Built-In Self Testing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output
IEEE Transactions on Computers
On Built-In Self-Test for Adders
Journal of Electronic Testing: Theory and Applications
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Abstract: A high-level fault modeling and testing philosophy is proposed which is aimed at ensuring full detection of low level, physical faults, as well as the industry-standard single stuck-line (SSL) faults. A set of independent functional faults and the corresponding functional tests are derived (induced) from the circuit under test; of particular interest are SSL-induced functional faults or SIFs. We present, for the first time, complete functional circuit models and tests for representative 74X-series and ISCAS-85 benchmark circuits, and apply the proposed methodology to them. These examples demonstrate that functional testing can, with far less effort than conventional method, produce test sets that provide complete coverage of SSL faults in practical circuits. Surprisingly, these test sets are also provably of minimal or near-minimal size.