Scalable Test Generators for High-Speed Datapath Circuits

Authors:
Hussain Al-Asaad;John P. Hayes;Brian T. Murray
Affiliations:
Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, The University of Michigan, 1301 Beal Avenue, Ann Arbor, MI 48109-2122.;Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, The University of Michigan, 1301 Beal Avenue, Ann Arbor, MI 48109-2122.;Electrical and Electronics Department, General Motors R&D Center, 30500 Mound Road, Warren, MI 48090-9055
Venue:
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Year:
1998

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Abstract

This paper explores the design of efficient test sets andtest-pattern generators for on-line BIST. The targetapplications are high-performance, scalable datapath circuits for which fast and complete fault coverage is required.Because of the presence of carry-lookahead, most existingBIST methods are unsuitable for these applications.High-level models are used to identify potential test sets for asmall version of the circuit to be tested. Then a regular test setis extracted and a test generator TG isdesigned to meet the following goals: scalability, small test setsize, full fault coverage, and very low hardware overhead. TG takesthe form of a twisted ring counter with a small decoder array. Weapply our technique to various datapath circuitsincluding a carry-lookahead adder, an arithmetic-logicunit, and a multiplier-adder.