Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Efficient UBIST implementation for microprocessor sequencing parts
Journal of Electronic Testing: Theory and Applications
Theory of Transparent BIST for RAMs
IEEE Transactions on Computers
Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Software Fault Tolerance
Concurrent Error Detection Using Watchdog Processors-A Survey
IEEE Transactions on Computers
Proceedings of the IEEE International Test Conference
Online and Offline BIST in IP-Core Design
IEEE Design & Test
A Fault Tolerant Approach to Microprocessor Design
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
GRAAL: a Tool for Highly Dependable SRAMs Generation
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
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We survey online testing techniques in embedded systems and evaluate them based on the following parameters: error coverage, error latency, space redundancy, and time redundancy. We then discuss online BIST methods that provide full error coverage, bounded error latency, low space and time redundancy, and impose no redesign constraints on the circuit under test. Finally, we discuss a recently designed commercial microprocessor for critical applications that incorporate most of the methods considered.