Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
An overview of deterministic functional RAM chip testing
ACM Computing Surveys (CSUR)
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Tutorial on semiconductor memory testing
Journal of Electronic Testing: Theory and Applications - Special issue: on memory testing
Theory of Transparent BIST for RAMs
IEEE Transactions on Computers
Guest Editors' Introduction: Online VLSI Testing
IEEE Design & Test
Online BIST for Embedded Systems
IEEE Design & Test
On the Necessity of On-line-BIST in Safety-Critical Applications - A Case-Study
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
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This paper presents a tool to achieve proper reliabilitylevels in systems based on memories, allowing theautomatic insertion of BIST architectures for both OFF-lineand ON-line memory testing. While OFF-line memorytesting was partially targeted by the available commercialtools, ON-line memory testing was so far notcovered.The set of algorithms and architectures supported bythe tool is not limited, and it can be easily extended toinclude innovative architectures and achieve the reliabilityrequirements in any application. Using the tool, thedesigner can generate dependable memories trading-offin the design process dependability properties and costs.