Test Pattern Generation for API Faults in RAM
IEEE Transactions on Computers
Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
Theory of Transparent BIST for RAMs
IEEE Transactions on Computers
Detection of Delay Faults in Memory Address Decoders
Journal of Electronic Testing: Theory and Applications
Using March Tests to Test SRAMs
IEEE Design & Test
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
CrossCheck: An Innovative Testability Solution
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Industrial BIST of Embedded RAMs
IEEE Design & Test
Hypergraph Coloring and Reconfigured RAM Testing
IEEE Transactions on Computers
Functional test for shifting-type FIFOs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Towards a Uniform Notation for Memory Tests
EDTC '96 Proceedings of the 1996 European conference on Design and Test
GRAAL: a Tool for Highly Dependable SRAMs Generation
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Built in self testing for detection of coupling faults in semiconductor memories
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
An On-Line BISTed SRAM IP Core
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A simple diagnostic method for memory testing
ICECS'03 Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing
An accumulator-based compaction scheme for online BIST of RAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the application of the concept of dependability for design and analysis of vision systems
ICVS'03 Proceedings of the 3rd international conference on Computer vision systems
Aliasing-free signature analysis for RAM BIST
ITC'94 Proceedings of the 1994 international conference on Test
Generating march tests automatically
ITC'94 Proceedings of the 1994 international conference on Test
An efficient fault detection algorithm for NAND flash memory
ACM SIGAPP Applied Computing Review
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This paper presents an overview of deterministic functional RAM chip testing. Instead of the traditional ad-hoc approach toward developing memory test algorithms, a hierarchy of functional faults and tests is presented, which is shown to cover all likely functional memory faults. This is done by presenting a novel way of categorizing the faults. All (possible) fault combinations are discussed. Requirements are put forward under which conditions a fault combination can be detected. Finally, memory test algorithms that satisfy the given requirements are presented.