Random Pattern Testing Versus Deterministic Testing of RAMs
IEEE Transactions on Computers
An overview of deterministic functional RAM chip testing
ACM Computing Surveys (CSUR)
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
LSSD Compatible and Concurrently Testable Ram
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
High Quality Testing of Embedded RAMs Using Circular Self-Test Path
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Fault tolerant and BIST design of a FIFO cell
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Processor-programmable memory BIST for bus-connected embedded memories
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM
Journal of Electronic Testing: Theory and Applications
Integrating Online and Offline Testing of a Switching Memory
IEEE Design & Test
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study
EDTC '96 Proceedings of the 1996 European conference on Design and Test
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
BIST design optimization for large-scale embedded memory cores
Proceedings of the 2009 International Conference on Computer-Aided Design
Diagnosis of MRAM write disturbance fault
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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High-quality memory testing is increasingly important, especially when RAMs and ROMs are deeply embedded in bigger systems, as the techniques based on control and observation points fail. Adopting a built-in self-test scheme for deeply embedded memories seems advantageous and industrial experience at Italtel, a telecom company, confirms it. The scheme implements in hardware the test pattern generation algorithm proposed by R. Nair, S.M. Thatte, and J.A. Abraham \cite{NTAb78}, extending it to word-based memories. Area overhead, performance degradation, additional pins, and test time are minimal, whereas we guarantee high fault coverage for the significant failure modes and full testability of the BIST hardware, as the experimental results confirm.