Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
On programmable memory built-in self test architectures
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Processor-programmable memory BIST for bus-connected embedded memories
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Industrial BIST of Embedded RAMs
IEEE Design & Test
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
Built-In Self-Test for Multi-Port RAMs
ATS '97 Proceedings of the 6th Asian Test Symposium
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures
IEEE Communications Magazine
Particle swarm optimization based BIST design for memory cores in mesh based network-on-chip
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
| Hi-index | 0.00 |
Built-in Self Test (BIST) is a crucial technique for testing embedded memory cores in a System-on-Chip (SoC). However, there is not much published work on BIST design optimization for multiple memory cores in the SoC designs. In this paper, we present a method for the BIST design optimization problem for large-scale SoC embedded memory cores, considering various real-world constraints such as peak current, IR drop, etc. Our method is based on a three-stage technique: (1) assignment, (2) legalization, and (3) refinement. The first stage adopts an integer linear programming (ILP) formulation for each memory partition to find a desired assignment of memory cores to controllers. The second stage then legalizes the assignment to meet user-specified assignment constraints. The last stage refines the solution to further reduce its cost. Experimental results show that our method can reduce the test time by 26.6%, the routing length by 8.9%, and the area by 24.1%, compared with a heuristic method currently used in industry.