Processor-programmable memory BIST for bus-connected embedded memories

Authors:
Ching-Hong Tsai;Cheng-Wen Wu
Affiliations:
Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC;Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

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Abstract

We present a processor-programmable built-in self-test (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circuit can be programmed via an on-chip microprocessor. Upon receiving the commands from the microprocessor, the BIST circuit generates pre-defined test patterns and compares the memory outputs with the expected outputs. Most popular memory test algorithms can be realized by properly programming the BIST circuit using the processor instructions. Compared with processor-based memory BIST schemes that use an assembly-language program to generate test patterns and compare the memory outputs, the test time of the proposed memory BIST scheme is greatly reduced.