IEEE Design & Test
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
Design-for-Iddq-Testing for Embedded Cores Based System-on-a-Chip
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Testability strategy of the Alpha AXP 21164 microprocessor
ITC'94 Proceedings of the 1994 international conference on Test
Processor-programmable memory BIST for bus-connected embedded memories
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores
Journal of Electronic Testing: Theory and Applications
BIST Technique by Equally Spaced Test Vector Sequences
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Matrix-based software test data decompression for systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Hardware/Software Co-testing of Embedded Memories in Complex SOCs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
2.5D system integration: a design driven system implementation schema
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Extending boundary-scan to perform a memory built-in self-test
ICC'05 Proceedings of the 9th International Conference on Circuits
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2.5-Dimensional VLSI system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Deterministic test vector compression / decompression using an embedded processor
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
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In this paper, we describe the testmethodology for embedded cores basedsystem-on-a-chip (SoC) which contains amicroprocessor core. First the microprocessorcore is tested for correctness of all theinstructions and then the computation powerof the microprocessor core is used to test theon-chip memories and other cores. A smallIddq test set is also used to detect physicaldefects, the design features to facilitate Iddqtesting are described.