Deterministic test vector compression / decompression using an embedded processor

Authors:
Maciej Bellos;Dimitris Nikolos
Affiliations:
Technology and Computer Architecture Laboratory, Dept. of Computer Engineering & Informatics, University of Patras, Patras, Greece;Research Academic Computer Technology Institute, Patras, Greece
Venue:
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Year:
2005

Citing 21
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Abstract

Test data compression and on-chip decompression using an embedded processor has already been proposed for test data volume and test time reduction as well as for use of slower testers without decreasing test quality. On the other hand, scan cell reordering methods have been proposed to overcome the problem of high average power dissipation during scan based external testing. In this paper we propose a scan cell ordering based test vector compression method, which reduces test data volume up to 87.3%. The decompression of the test data is based on the use of an embedded processor.