HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Test Resource Partitioning for SOCs
IEEE Design & Test
A Methodology to Design Efficient BIST Test Pattern Generators
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets
ATS '99 Proceedings of the 8th Asian Test Symposium
Test Compaction in a Parallel Access Scan Environment
ATS '97 Proceedings of the 6th Asian Test Symposium
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
ATS '98 Proceedings of the 7th Asian Test Symposium
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Transformed pseudo-random patterns for BIST
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Design of built-in test generator circuits using width compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test data compression and decompression based on internal scan chains and Golomb coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design space exploration for aggressive test cost reduction in CircularScan architectures
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Survey of Test Vector Compression Techniques
IEEE Design & Test
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Scan power reduction in linear test data compression scheme
Proceedings of the 2009 International Conference on Computer-Aided Design
Time-multiplexed compressed test of SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
Test data compression based on geometric shapes
Computers and Electrical Engineering
Deterministic test vector compression / decompression using an embedded processor
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scan power reduction for linear test compression schemes through seed selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
A test pattern compression scheme for test data volume and application time reduction is proposed. While compression reduces test data volume, the increased number of internal scan chains due to an on-chip, fixed-rate decompressor reduces test application time proportionately. Through on-chip decompression, both the number of virtual scan chains visible to the ATE and the functionality of the ATE are retained intact. Complete fault coverage is guaranteed by constructing the decompression hardware deterministically through analysis of the test pattern set.