IEEE Transactions on Computers
Efficient test-data compression for IP cores using multilevel Huffman coding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Multilevel-Huffman test-data compression for IP cores with multiple scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan-chain partition for high test-data compressibility and low shift power under routing constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computers and Electrical Engineering
LFSR-based test-data compression with self-stoppable seeds
Proceedings of the Conference on Design, Automation and Test in Europe
Time-multiplexed compressed test of SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a data compression method and decompression architecture for testing embedded cores in a system-on-a-chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chain(s) of the core under test and provides significantly better results than a recent compression method that uses Golomb coding and a separate cyclical scan register (CSR). The major advantages of Golomb coding of test data include very high compression, analytically predictable compression results, and a low-cost and scalable on-chip decoder. The use of the internal scan chain for decompression obviates the need for a CSR, thereby reducing hardware overhead considerably. In addition, the novel interleaving decompression architecture allows multiple cores in an SOC to be tested concurrently using a single ATE I/O channel. We demonstrate the effectiveness of the proposed approach by. applying it to the ISCAS 89 benchmark circuits