A case study on the implementation of the Illinois Scan Architecture
Proceedings of the IEEE International Test Conference 2001
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Test Data Compression Using Dictionaries with Fixed-Length Indices
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Efficient Seed Utilization for Reseeding based Compression
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computers
XMAX: X-Tolerant Architecture for MAXimal Test Compression
ICCD '03 Proceedings of the 21st International Conference on Computer Design
IEEE Transactions on Computers
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Relating Entropy Theory to Test Data Compression
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multiple Scan Tree Design with Test Vector Modification
ATS '04 Proceedings of the 13th Asian Test Symposium
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion
ITC '04 Proceedings of the International Test Conference on International Test Conference
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Proceedings of the conference on Design, automation and test in Europe
Automated synthesis of phase shifters for built-in self-test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test data compression and decompression based on internal scan chains and Golomb coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test data compression based on input-output dependence
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ring generators - new devices for embedded test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we observe that the necessary amount of compressed test data transferred from the tester to the embedded cores in a system-on-a-chip (SOC) varies significantly during the testing process. This motivates a novel approach to compressed system-on-a-chip testing based on time-multiplexing the tester channels. It is shown how the introduction of a few control channels will enable the sharing of data channels, on which compressed seeds are passed to every embedded core. Through the use of modular and scalable hardware for on-chip test control and test data decompression, we define a new algorithmic framework for test data compression that is applicable to system-on-a-chip devices comprising intellectual property-protected blocks.