Test data compression technique for embedded cores using virtual scan chains

Authors:
Abhijit Jas;Bahram Pouya;Nur A. Touba
Affiliations:
Intel Corporation, Austin, TX and Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX;Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX;Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

Citing 18
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Abstract

This paper presents a design-for-test (DFT) technique to implement a "virtual scan chain" in a core that looks (to the system integrator) like it is shorter than the real scan chain inside the core. A core with a "virtual scan chain" is fully compatible with a core with a regular scan chain in terms of both the external test interface and tester program. The I/O pins of a core with a virtual scan chain are identical to the I/O pins of a core with a regular scan chain. For the system integrator, testing a core with a virtual scan chain is identical to testing a core with a regular scan chain (no special modes, control signals, or timing sequences are needed). The only difference is that the virtual scan chain is much shorter so the size of the scan vectors and output response is smaller resulting in less test data as well as less test time (fewer scan shift cycles). The process of mapping the virtual scan vectors to real scan vectors is handled inside the core and is completely transparent to the system integrator.