Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Combining low-power scan testing and test data compression for system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs
Proceedings of the conference on Design, automation and test in Europe
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
A Gated Clock Scheme for Low Power Scan-Based BIST
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Test Data Compression: The System Integrator's Perspective
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Relating Entropy Theory to Test Data Compression
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power Test Data Compression Based on LFSR Reseeding
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Low Power Test Compression Technique for Designs with Multiple Scan Chain
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
A cocktail approach on random access scan toward low power and high efficiency test
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified approach to reduce SOC test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
QC-fill: an X-fill method for quick-and-cool scan test
Proceedings of the Conference on Design, Automation and Test in Europe
Test data compression using alternating variable run-length code
Integration, the VLSI Journal
Test data compression for noc based socs using binary arithmetic operations
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Single cycle access structure for logic test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The random-like filling strategy pursuing high compression for today's popular test compression schemes introduces large test power. To achieve high compression in conjunction with reducing test power for multiple-scan-chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple-scan-chain designs. The scheme utilizes a decoding buffer, which supports fast loading using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied automatic test pattern generation (ATPG)-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with only a small area design overhead.