Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Test Resource Partitioning for SOCs
IEEE Design & Test
Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits
Journal of Electronic Testing: Theory and Applications
On test data compression and n-detection test sets
Proceedings of the 40th annual Design Automation Conference
A Case Study on t e Implementation of t e Illinois Scan Architecture
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On test data volume reduction for multiple scan chain designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
Matrix-based software test data decompression for systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Test data compression technique using selective don't-care identification
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Test Data Compression: The System Integrator's Perspective
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evolutionary Optimization in Code-Based Test Compression
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Evaluation of Error-Resilience for Reliable Compression of Test Data
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Enhancing error resilience for reliable compression of VLSI test data
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Efficient techniques for transition testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A Huffman-based coding with efficient test application
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On test data compression using selective don't-care identification
Journal of Computer Science and Technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A selective pattern-compression scheme for power and test-data reduction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A Test Data Compression Scheme for Reducing Power Based on OLELC and NBET
ICIC '08 Proceedings of the 4th international conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications - with Aspects of Theoretical and Methodological Issues
A Variable-Length Coding Adjustable for Compressed Test Application
IEICE - Transactions on Information and Systems
An Architecture of Embedded Decompressor with Reconfigurability for Test Compression
IEICE - Transactions on Information and Systems
A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs
IEICE - Transactions on Information and Systems
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On reducing test power and test volume by selective pattern compression schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MICRO: a new hybrid test data compression/ decompression scheme
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Data Compression Using Selective Sparse Storage
Journal of Electronic Testing: Theory and Applications
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Test data compression using four-coded and sparse storage for testing embedded core
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Virtual scan chains reordering using a RAM-based module for high test compression
Microelectronics Journal
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
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We showed recently that Golomb codes can be used for efficiently compressing system-on-a-chip test data. We now present a new class of variable-to-variable-length compression codes that are designed using the distributions of the runs of 0s in typical test sequences. We refer to these as frequency-directed run-length (FDR) codes. We present experimental results for the ISCAS 89 benchmark circuits to show that FDR codes outperform Golomb codes for test data compression. We also present a decompression architecture for FDR codes, and an analytical characterization of the amount of compression that can be expected using these codes. Analytical results show that FDR codes are robust, i.e. they are insensitive to variations in the input data stream.