Proceedings of the conference on Design, automation and test in Europe
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Data Compression for System-on-a-Chip Using Golomb Codes
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
Proceedings of the conference on Design, automation and test in Europe
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
How Effective are Compression Codes for Reducing Test Data Volume?
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computers
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Relating Entropy Theory to Test Data Compression
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Journal of Electronic Testing: Theory and Applications
Survey of Test Vector Compression Techniques
IEEE Design & Test
Test Data Compression by Spilt-VIHC (SVIHC)
ICCTA '07 Proceedings of the International Conference on Computing: Theory and Applications
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs
IEEE Transactions on Computers
Test data compression scheme based on variable-to-fixed-plus-variable-length coding
Journal of Systems Architecture: the EUROMICRO Journal
RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Combined Partial Test Vector Reuse and FDR Coding for Two Dimensional SoC Test Compression
ICICSE '08 Proceedings of the 2008 International Conference on Internet Computing in Science and Engineering
Survey of Test Data Compression Technique Emphasizing Code Based Schemes
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
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The run length based coding schemes have been very effective for the test data compression in case of current generation SoCs with a large number of IP cores. The first part of paper presents a survey of the run length based codes. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In the second part of the paper, the five different approaches for "don't care" bit filling based on nature of runs are proposed to predict the maximum compression based on entropy. Here the various run length based schemes are compared with maximum data compression limit based on entropy bounds. The actual compressions claimed by the authors are also compared. For various ISCAS circuits, it has been shown that when the X filling is done considering runs of zeros followed by one as well as runs of ones followed by zero (i.e., Extended FDR), it provides the maximum data compression. In third part, it has been shown that the average test power and peak power is minimum when the don't care bits are filled to make the long runs of 0s as well as 1s.