RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power

Authors:
Hao Fang;Chenguang Tong;Xu Cheng
Affiliations:
Micro Processor Research and Development Center of Peking University, Beijing, China, 100871. Tel: 0;Micro Processor Research and Development Center of Peking University, Beijing, China, 100871. Tel: 0;Micro Processor Research and Development Center of Peking University, Beijing, China, 100871. Tel: 0
Venue:
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Year:
2007

Citing 0
Cited 3

Run-length-based test data compression techniques: how far from entropy and power bounds?—a survey

VLSI Design
Weighted transition based reordering, columnwise bit filling, and difference vector: a power-aware test data compression method

VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
A modified scheme for simultaneous reduction of test data volume and testing power

VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test

Quantified Score

Hi-index	0.00

Visualization

Abstract

As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequency-directed run-length (EFDR) is one of the best coding compression schemes. In this paper, we present a novel algorithm named RunBasedReordering(RBR), which is based on EFDR codes. Three techniques have been applied to this algorithm: scan chain reordering, scan polarity adjustment and test pattern reordering. The experiment results show that the test data compression ratio is significantly improved and scan power consumption is dramatically reduced. Moreover, our algorithm can be easily integrated into the existing industrial flow with little area penalty.