Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
IEEE Transactions on Computers
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Survey of Test Vector Compression Techniques
IEEE Design & Test
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Optimal Selective Huffman Coding for Test-Data Compression
IEEE Transactions on Computers
RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories
IEEE Design & Test
Efficient Don't Care Filling for Power Reduction during Testing
ARTCOM '09 Proceedings of the 2009 International Conference on Advances in Recent Technologies in Communication and Computing
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Test data compression using alternating variable run-length code
Integration, the VLSI Journal
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Today's electronic systems, with ever-growing demand for mobile computing devices, are more complex, fast and energy efficient. Cost and quality are the major issues in testing these circuits. The test data storage requirements, along with the operating frequency and channel capacity, have a significant impact on the test cost. This paper presents a new compression scheme based on Alternating Variable Run-length (AVR) codes for reducing the test data. Weighted transition based reordering scheme is adopted prior to the compression scheme to improve the compression ratio (CR). By applying an appropriate mapping scheme, sufficient reduction in power has been achieved. The scheme is also found to have a maximum of 10% increase in compression ratio when compared to the conventional frequency directed run-length codes (FDR) codes and extended FDR (EFDR) codes without any significant on-chip area overhead. The experiments are performed on ISCAS'89 benchmark circuits.