Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Combining low-power scan testing and test data compression for system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
High Defect Coverage with Low-Power Test Sequences in a BIST Environment
IEEE Design & Test
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
A token scan architecture for low power testing
Proceedings of the IEEE International Test Conference 2001
Peak-power reduction for multiple-scan circuits during test application
ATS '00 Proceedings of the 9th Asian Test Symposium
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Power Driven Chaining of Flip-Flops in Scan Architectures
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Power Reduction in Test-Per-Scan BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test Power Reduction through Minimization of Scan Chain Transitions
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Controlling Peak Power During Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Low Power Test Data Compression Based on LFSR Reseeding
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Jump Scan: A DFT Technique for Low Power Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Partial Gating Optimization for Power Reduction During Test Application
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Survey of Test Vector Compression Techniques
IEEE Design & Test
Low Power Embedded Deterministic Test
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Bounded Adjacent Fill for Low Capture Power Scan Testing
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan testing and test data compression for system-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DS-LFSR: a BIST TPG for low switching activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An automatic test pattern generator for minimizing switching activity during scan testing activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified approach to reduce SOC test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LT-RTPG: a new test-per-scan BIST TPG for low switching activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Low-power test in compression-based reconfigurable scan architectures
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Test data compression using alternating variable run-length code
Integration, the VLSI Journal
Test Data Compression Using Selective Sparse Storage
Journal of Electronic Testing: Theory and Applications
Test data compression using interval broadcast scan for embedded cores
Microelectronics Journal
Achieving low capture and shift power in linear decompressor-based test compression environment
Microelectronics Journal
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs
Proceedings of the International Conference on Computer-Aided Design
A modified scheme for simultaneous reduction of test data volume and testing power
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during all phases of scan test: loading, capture, and unloading. In particular, we introduce a new on-chip continuous-flow decompressor. Its synergistic use with a poweraware scan controller allows a significant reduction of toggling rates when feeding scan chains with decompressed test patterns. While the proposed solution requires minimal modifications of the existing design for test logic, experiments indicate that its use results in a low switching activity which reduces power consumption to or below a level of a functional mode. It resolves problems related to power dissipation, voltage drop, and increased temperature. Our approach integrates seamlessly with test logic synthesis flow, and it does not compromise compression ratios. It fits well into various design paradigms, including modular design flow where blocks come with individual decompressors and compactors.