A token scan architecture for low power testing

New test data decompressor for low power applications

Proceedings of the 44th annual Design Automation Conference

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Low-power scan operation in test compression environment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

On reducing scan shift activity at RTL

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes

ACM Transactions on Design Automation of Electronic Systems (TODAES)