Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
A token scan architecture for low power testing
Proceedings of the IEEE International Test Conference 2001
Inserting Test Points to Control Peak Power During Scan Testing
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
MD-SCAN Method for Low Power Scan Testing
ATS '02 Proceedings of the 11th Asian Test Symposium
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
Test Power Reduction through Minimization of Scan Chain Transitions
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Jump Scan: A DFT Technique for Low Power Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Partial Gating Optimization for Power Reduction During Test Application
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
An Efficient Peak Power Reduction Technique for Scan Testing
ATS '07 Proceedings of the 16th Asian Test Symposium
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells
Journal of Electronic Testing: Theory and Applications
Bounded Adjacent Fill for Low Capture Power Scan Testing
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Reducing Scan Shift Power at RTL
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
DCScan: A Power-Aware Scan Testing Architecture
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Dynamic scan chain partitioning for reducing peak shift power during test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan testing for test data compression using a routing-driven scan architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An automatic test pattern generator for minimizing switching activity during scan testing activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power dissipation in digital circuits during scan-based test is generally much higher than that during functional operation. Unfortunately, this increased test power can create hot spots that may damage the silicon, the bonding wires, and even the package. It can also cause intensive erosion of conductors-severely decreasing the reliability of a device. Finally, excessive test power may also result in extra yield loss. To address these issues, this paper first presents a detailed investigation of a benchmark circuit's switching activity during different modes of operation. Specifically, the average number of transitions in the combinational logic of a benchmark circuit during scan shift is found to be approximately 2.5 times more than the average number of transitions during the circuit's normal functional operation. A DFT-based approach for reducing circuit switching activity during scan shift is proposed. Instead of inserting additional logic at the gate level that may introduce additional delay on critical paths, the proposed method modifies the design at the register transfer level (RTL) and uses the synthesis tools to automatically deal with timing analysis and optimization. Our experiments show that significant power reduction can be achieved with very low overhead.