Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Scan Architecture for Shift and Capture Cycle Power Reduction
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
ATS '99 Proceedings of the 8th Asian Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On test generation for transition faults with minimized peak power dissipation
Proceedings of the 41st annual Design Automation Conference
Test Power Reduction with Multiple Capture Orders
ATS '04 Proceedings of the 13th Asian Test Symposium
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
IEEE Design & Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests
Proceedings of the conference on Design, automation and test in Europe
Scan-Based Tests with Low Switching Activity
IEEE Design & Test
Variation-Tolerant, Power-Safe Pattern Generation
IEEE Design & Test
Methodology for low power test pattern generation using activity threshold control logic
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Guided test generation for isolation and detection of embedded trojans in ics
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing
Journal of Electronic Testing: Theory and Applications
Opposite-phase register switching for peak current minimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A Novel ATPG Method for Capture Power Reduction during Scan Testing
IEICE - Transactions on Information and Systems
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Minimizing soft errors in TCAM devices: a probabilistic approach to determining scrubbing intervals
IEEE Transactions on Circuits and Systems Part I: Regular Papers
On reducing scan shift activity at RTL
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect aware X-filling for low-power scan testing
Proceedings of the Conference on Design, Automation and Test in Europe
Improved weight assignment for logic switching activity during at-speed test pattern generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Reducing the switching activity of test sequences under transparent-scan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Switching activity as a test compaction heuristic for transition faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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This paper presents a Progressive Match Filling (PMF) technique to reduce the peak current and power dissipation during the fast capture cycle in broadside delay fault testing. The proposed method fills the unspecified values (X) in the generated initialization vector such that the resulting launch vector at a minimal Hamming distance from the initialization vector. The proposed method does not require any hardware modification and can be used to obtain any test sets that require two pattern tests. Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISCAS 89 circuits.