Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

  • Authors:
  • Xiaoqing Wen;Kohei Miyase;Tatsuya Suzuki;Seiji Kajihara;Laung-Terng Wang;Kewal K. Saluja;Kozo Kinoshita

  • Affiliations:
  • Kyushu Institute of Technology, Iizuka, Japan 820-8502;Kyushu Institute of Technology, Iizuka, Japan 820-8502;Denso Techno Co., Nagoya, Japan 450-0002;Kyushu Institute of Technology, Iizuka, Japan 820-8502;SynTest Technologies, Inc., Sunnyvale, USA;University of Wisconsin---Madison, Madison, USA 53706;Osaka Gakuin University, Suita, Japan 564-8511

  • Venue:
  • Journal of Electronic Testing: Theory and Applications
  • Year:
  • 2008

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Abstract

At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However, at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity. This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage loss, and additional design effort.